1. Field of the Invention
The invention relates to a resistor positioned on a semiconductor wafer, and more particularly, to a semiconductor resistor for withstanding high voltages.
2. Description of the Prior Art
Resistors used in a high voltage circuits, such as radio frequency integrated circuits (RFIC), microwave frequency integrated circuits, or high power integrated circuits, are typically formed in a rectangular-shaped spiral and have a large surface area. This enables them to withstand high voltages.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a perspective diagram of a prior art semiconductor resistor 10 for withstanding high voltages. FIG. 2 is a top view diagram of the doped layer 14 shown in FIG. 1. The semiconductor resistor 10 comprises a Si substrate 12 with dopants characterizing it as an n-type semiconductor, a doped layer 14 with dopants characterizing it as a p-type semiconductor that functions as a resistor layer in a predetermined area on the silicon substrate 12, a dielectric layer 16 positioned on the silicon substrate 12 above the doped layer 14, and a passivation layer 18 positioned on the dielectric layer 16. The junction of the doped layer 14 and the silicon substrate 12 forms a pn-junction to prevent electrical leakage.
The resistor 10 is produced by implanting ions in a predetermined area on the silicon substrate 12 to form the doped layer 14 as a p-type semiconductor. As shown in FIG. 2, the doped layer 14 is formed in a rectangular-shaped spiral in which the doped layer 14 traces a rectangular path as it turns in on itself. The dielectric layer 16 is then deposited onto the silicon substrate 12 and doped layer 14. Contact windows (not shown) are formed at the two ends of the resistor 10 using photolithography and etching. Conduct windows are used to connect the resistor 10 with other components on the chip. Finally, the passivation layer 18 is deposited on the surface of the resistor 10.
With the deposition of the passivation layer 18, some charged ions are mixed with the depositing particles, and a plurality of fixed charges at fixed positions are generated. An electric field is generated by the charges of the passivation layer 18 when the resistor 10 is connected. This reduces the breakdown voltage of the pn-junction of the silicon substrate 12 and the doped layer 14 and generates electrical leakage. Since the doped layer 14 is formed on the silicon substrate 12 in a rectangular-shaped spiral structure, it forms right-angle corners. When the resistor 10 is used at high voltages, a strong electric field is generated at a right-angled corner of the doped layer 14. This reduces the voltage value of the resistor 10.